1. Field of the Invention
The present invention relates to a circuit for generating a horizontal synchronizing signal having a horizontal frequency determined by video synchronizing signal standards from a composite synchronizing signal.
2. Description of the Background Art
FIG. 24 illustrates a conventional horizontal synchronizing signal generating circuit which is disclosed in "Transistor Gijyutsu Special No. 5, P. 92, published on Sep. 10, 1987, CQ Publishing & Co., Ltd."
Referring to FIG. 24, the reference numerals 71, 73, 74, 77 designate inverter circuits; 72 designates a resistor; 70 designates a capacitor; 75, 79, 80 designate flip-flop circuits; 76 designates a 4-bit counter circuit; and 78 designates an NAND circuit.
In operation, a clock (small-signal sine wave) entered at an input terminal Te is subjected to the removal of DC elements therefrom by the capacitor 70, amplified by an amplifier including the resistor 72 and the inverter circuit 71, and then waveform-shaped by the inverter circuit 73 into a rectangular-wave clock.
Then the clock is frequency-divided by two by the flip-flop circuit 75, and the frequency-divided clock is entered into the counter circuit 76. The counter circuit 76 performs a count-up operation in synchronism with the entered clock. Outputs from the counter circuit 76 are applied to the NAND circuit 78. The NAND circuit 78 decodes the outputs from the counter circuit 76 and drives its output low just at the time when the counter value becomes E.sub.H. An output signal from the NAND circuit 78 resets the flip-flop 79. After the reset is cancelled, an output Q of the flip-flop circuit 79 is set to "H" at the falling edge of a composite synchronizing signal entered at an input terminal Td and polarity-inverted by the inverter circuit 74. An output Q of the flip-flop circuit 80 on the next stage is set to "H" level at the rising edge of an output signal from the flip-flop circuit 79. At the same time, the output signal from the flip-flop circuit 79 cancels a reset signal of the counter circuit 76, pertaining the counter circuit 76 to restart the counter operation.
The least significant bit signal in a count output signal from the counter circuit 76 is entered into the inverter circuit 77 which in turn inverts the polarity of the least significant bit signal to input the inverted signal to a reset terminal R of the flip-flop circuit 80. Consequently, the flip-flop circuit 80 is reset just at the time when the count value becomes 1.sub.H after the restart of the count operation of the counter circuit 76. The above described sequence of operations are carried out successively, and a horizontal synchronizing signal is outputted from an output terminal Tf of the flip-flop circuit 80.
In the conventional circuit arrangement, however, the stability of the horizontal synchronizing signal to be generated depends on the states of the entered composite synchronizing signal. That is, when the horizontal frequency of the entered composite synchronizing signal is varied in such a manner that it is higher or lower than the horizontal frequency determined by the video synchronizing signal standards (the composite synchronizing signal at this time is referred to as a nonstandard signal), the horizontal frequency of the generated horizontal synchronizing signal also varies relative to the horizontal frequency of the video synchronizing signal standards since the horizontal synchronizing signal is generated in synchronism with the detected falling edge of the entered composite synchronizing signal as above stated.
Further, the conventional circuit has the drawback that the horizontal synchronizing signal is not generated in the absence of the composite synchronizing signal. Therefore, it has been desired to accomplish a circuit which can generate the horizontal synchronizing signal with high stability in the absence of the composite synchronizing signal.